Leveraging years of collective industry best practices, the Verification Methodology Manual for Low Power (VMM-LP) introduces a new verification methodology for low power and provides a blueprint for successful verification of low power designs. It describes the common causes of low power design failures, the impact of low power on the specification of power intent, the implementation of test plans, the setup of testbenches and the metrics of verification using assertions and coverage. The VMM-LP builds on the base classes in industry standard VMM to enable the deployment of a consistent, reusable, and scalable power-aware verification environment across multiple design projects within a company. In addition to benefitting from the extensive practical experience of the authors from ARM, Synopsys, and Renesas, the VMM-LP is also peer-reviewed by more than 30 low power design and verification experts from around the world.
About Srikanth JadcherlaSee more books from this Author